`include "/home/lab/lab14/Computer_architecture/homwork/full_adder/src/full_adder1.v"
module full_adder16 (
    input [15:0] OP_A,
    input [15:0] OP_B,
    input CYI ,

    output  CYO,
    output [15:0] SUM
);

wire [15:0] co_temp;

full_adder u_adder0 (
    .A(OP_A[0]),
    .B(OP_B[0]),
    .CYI(CYI),
    .SUM(SUM[0]),
    .CYO(co_temp[0])
);

genvar i ;

generate 
    for (i=1;i<=15;i=i+1) begin
        full_adder u_adder (
            .A(OP_A[i]),
            .B(OP_B[i]),
            .CYI(co_temp[i-1]),
            .SUM(SUM[i]),
            .CYO(co_temp[i])
        );
    end 
endgenerate

assign CYO = co_temp[15];
    
endmodule
